What switching/routing path processes policy routing entries?

I notice when you use interface level <IP policy route-map> and global <ip local policy route-map>  the entries are not in the normal routing table. What routing table or path handles these? Control Plane....subinterface...CEF Switching etc....what exactly happens?

Comments

  • On most platforms, certainly for the CCIE exam, these would be processed by the CPU.  Some of the higher end devices can do policy routing in hardware as long as you restrict the policy to specific commands, otherwise PBR is punted to the CPU for those also.  

     

    Nick

  • Thanks Nick. 

    But exactly what table do they use for forwarding...that would show how say you would see show ip route output for a normal route?

    Also at the CPU I'm assuming its control plane traffic. Would that be an example of control plane host subinterface for <Ip local policy> locally originated .....and ..... control plane transit subinterface for the interface level <ip policy>...being transit traffic via the router or is my understanding skewed.....this is a little bit of speculative arena for me....

  • Nick,

    Everything is processed by CPU on software platforms like 38xx. But some traffic is processed in interupt handler (CEF switching mode), some traffic is processed using route-cache (I hope it's almost gone now), some traffic is proccessed by process switching.

     

    So the main question is: Is the policy routing traffic processed in interrupt mode as CEF (quick mode) or in process switching (slow and processor consuming mode).

     

    Thanks

  • peetypeety ✭✭✭

    But exactly what table do they use for forwarding...that would show how say you would see show ip route output for a normal route?

    The router will use the process switching path, and it will use the route map referenced in the PBR statement.  It can't necessarily use a table; normal routing is based solely on the destination L3 address, whereas PBR can use anything (L3, L4) on the source side and/or anything (L3, L4) on the dest side.

    On bigger platforms with true separation of control and data plane, certain types of PBR (as mentioned above) are streamlined enough that the CEF path can still handle PBR, keeping things optimized.

    I'm curious: why the questions on this?  Are you fearing some sort of "how it works" question on the written or lab?

  • whereas PBR can use anything (L3, L4) on the source side and/or anything (L3, L4) on the dest side.

     

    As I remember PBR can also use packet length.

  • Thanks for the responses. My curiosity is beyond the actual exam. I like to know how things actually work...

  • Thanks for the responses. My curiosity is beyond the actual exam. I like to know how things actually work...

     

    Honestly I'd suggest to check the answer by experiment. Because if PBR works through process switching it have to be SLOOOW. But I don't remember that my equipment was slow when I enabled PBR instead of a route table on 7206 10 years ago. So I suspect (but can't prove) that PBR is working in interrupt handler as CEF switching does.

  • Pchel, 

    I hazard that would be an interesting adventure...I'll give it a try through experimentation..Thanks.

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